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LMZ14201
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Simplified Application Schematic
SNVS649F – JANUARY 2010 – REVISED OCTOBER 2013
V IN
LMZ14201
V OUT
5V
3.3V
2.5V
1.8V
1.5V
1.2V
0.8V
R FBT
5.62k
3.32k
2.26k
1.87k
1.00k
4.22k
0
R FBB
1.07k
1.07k
1.07k
1.50k
1.13k
8.45k
39.2k
R ON
100k
61.9k
47.5k
32.4k
28.0k
22.6k
24.9k
V IN Range
7.5...42V
6...42V
6...30V
6...25V
6...21V
6...19V
6...18V
V OUT @ 1A
R ON
C FF
0.022 2 F
See Table
Enable
R FBT
See Table
C IN
10 2 F
C SS
0.022 2 F
R FBB
See Table
100 2 F
Connection Diagram
7
6
VOUT
FB
Exposed Pad
Connect to GND
5
4
3
2
1
SS
GND
EN
RON
VIN
Figure 2. Top View
7-Lead PFM
Pin Descriptions
Pin
1
2
3
4
5
6
7
EP
Name
VIN
RON
EN
GND
SS
FB
VOUT
EP
Description
Supply input — Nominal operating range is 6V to 42V . A small amount of internal capacitance is contained within the
package assembly. Additional external input capacitance is required between this pin and exposed pad.
On Time Resistor — An external resistor from V IN to this pin sets the on-time of the application. Typical values range from
25k to 124k ohms.
Enable — Input to the precision enable comparator. Rising threshold is 1.18V nominal; 90 mV hysteresis nominal.
Maximum recommended input level is 6.5V.
Ground — Reference point for all stated voltages. Must be externally connected to EP.
Soft-Start — An internal 8 μA current source charges an external capacitor to produce the soft-start function. This node is
discharged at 200 μA during disable, over-current, thermal shutdown and internal UVLO conditions.
Feedback — Internally connected to the regulation, over-voltage, and short-circuit comparators. The regulation reference
point is 0.8V at this input pin. Connected the feedback resistor divider between the output and ground to set the output
voltage.
Output Voltage — Output from the internal inductor. Connect the output capacitor between this pin and exposed pad.
Exposed Pad — Internally connected to pin 4. Used to dissipate heat from the package during operation. Must be
electrically connected to pin 4 external to the package.
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Copyright ? 2010–2013, Texas Instruments Incorporated
Product Folder Links: LMZ14201
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